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(I) VLSI Information Processing Algorithms and Architectures for Multimedia, Biomedical, and Communication Systems
1. Reconfigurable / Programmable 3D Graphics Processor: Algorithm and Architecture
i Sub-division/Phong/Gruraud Alaogirhtm
ii Depth-Buffer and Texture Compression Algorithm
iii Geometry Transformation and Rasterization
iv Bit/Instruction/Task-Level Parallel Computation

2. Adaptive Algorithms and Architectures
i GPGI/V-BLAST/Chase/Iterative Detection Algorithm
ii FastICA/INFORMAX Algorithm
iii LMS Algorithm / Delay LMS / Relaxed Look-ahead Algorithm
iv RLS / Relaxed-Givens Rotations (RGR) RLS Algorithm

3. Computer Arithmetic Algorithms and Architectures
i Baugh-Wooley Algorithm
ii Booth/Redundant Number System Algorithm
iii Square-root and Division Algorithm

4. Orthogonal Transform Algorithms and Architectures
i Multiplier-Accumulation Based Algorithm
ii Recursive Algorithm
iii ROM-Based Algorithm
iv Butterfly Based Algorithm

5. Systemes and Applications
i IoT/M2M: Plant-care System and Elevator
ii 3D Graphics (GPU) and GPGPU
iii EEG/EKG Biomedical Acquisition System

(II) VLSI Information Processing Chips for DSP and Communication Systems
Die Photo
(Initialized by CIC & NCKU and cooperate with CIC, NTU, NCKU, NSYSU, CCU)

MP-SOC Chip Post Simulation Results
Process Technology TSMC 0.13mm CMOS
Core Area 3700mm x 3700mm
Chip Area 4950mm x 4938mm
Clock Frequency 100 MHz
Instance Count DWT:948, AES:14700,
ME:72646, ATP1:18806,
ATP2:8837,
A7 RISC:22736,
SDCTIV:13228,
IMDCT:35507,
DCT-CP: 4769
64-Point Recursive FFT Processor Post Simulation Results
Input Wordlength 16-bit
Supply Voltage 1.3 V
Clock Frequency 50 MHz
Chip Size 1822 um X 1822 um
Process TSMC 0.13um
A Fine-Grain Pipeline 2-D DCT/IDCT Processor Measurement Results
Input Wordlength 12-bit
Output Wordlength 10-bit
Supply Voltage 1.3 V
Clock Frequency 250 MHz
Chip Size 0.42 mm2
Process UMC 0.13um
Baugh-Wooley Fixed-Width Multiplier Post Simulation Results
Input Wordlength 8-bit
Output Wordlength 8-bit
Supply Voltage 1.8 V
Clock Frequency 6.98 ns
Power 0.336 mW@100MHz
Chip Size 70.64 um X 70.52 um
Process UMC 0.18um
2-D Digital Filter for Image Restoration Post Simulation Results (Timemill)
Supply Voltage 3.3 V
Clock Frequency 66 MHz
Chip Size 3.0mm X 3.0mm
Gate Count 73710
Process TSMC 0.35um 1P4M
Package DIP with 40 pins
Last Updated at 12:24 Nov 23, 2016

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