Digital Systems Design

教學目標:

Introduce the fundamental concepts for the digital system design

課程綱要

Lecture 0 Syllabus

Lecture 7 Registers and Register Transfers

Lecture 8 Sequencing and Control

Lecture 9 Memory Basics

Lecture 10 Computer Design Basics

Lecture 11 Instruction Set Architecture

Lecture 12 RISC Central Processing Unit

DSD HW1&2 sol.

Reference Answers for Chapter 9

Reference Answers for Chapter 10 part-1

Reference Answers for Chapter 10 part-2

Reference Answers for Chapter 11

Reference Answers for Quiz 2

Reference Answers for Quiz 3

#Announcement DSD最後成績 ,請確認自己成績,如有問題請在7/2中午前與助教聯絡 Final_Score

#Announcement Midterm

#Announcement Midterm 2

#Announcement Final exam

   

News Content Deadline / Date
Hw 1 Problem 7.3, 7.7, 7.10 3/12, 2009
Hw 2 Problem 7.15, 7.16, 7.18 3/19, 2009
Hw 3 Problem 7.23, 7.26, 7.30 3/26, 2009
Hw 4 Problem 8.3, 8.8, 8.9 4/2, 2009
Update Lecture 8 3/26, 2009
HW Sol. HW1 & HW2 4/5, 2009
Midterm Lecture 7, 8, 9 (content before 4/7) AM10:10~AM12:00,4/14, 2009
Update Lecture 9 4/9, 2009
Update Lecture 10 4/20, 2009
Update Lecture 10 5/4, 2009
Update Lecture 10 5/7, 2009
Hw 6 Problem 10.3, 10.7, 10.8 5/12, 2009
Quiz 2 Lecture 9 AM9:00~AM9:50,5/14, 2009
Midterm 2 Lecture 9, 10 AM10:10~AM12:00,5/19, 2009
Update Lecture 11 5/20, 2009
Hw 7 Problem 10.9, 10.13, 10.16 5/26, 2009
Update Lecture 11 6/1, 2009
Update Lecture 11 6/2, 2009
Hw 8 Problem 11.1, 11.5, 11.11 6/16, 2009
Quiz 3 Lecture 11 AM10:10~AM11:20,6/16, 2009
Final exam Lecture 10, 11, 12(content before 6/11) AM10:10~AM12:00,6/23, 2009
Update Lecture 12 6/10, 2009
Update Lecture 12 6/15, 2009
Update Lecture 12 6/30, 2009

 

Teaching Assistant:

陳姵妤 pychen(at)viplab.cs.nctu.edu.tw

呂宗哲 tclu(at)viplab.cs.nctu.edu.tw

吳迪優 dywu(at)viplab.cs.nctu.edu.tw

Phone: 03-5712121-59283

Last Update: 6/30, 2009

Office Hour: 10:00AM~12:00AM Thursday