Digital Systems Design

教學目標

本課程以邏輯設計知識為基礎,探討數位系統的原理與設計。

課程綱要:

Lecture 0 Syllabus

Lecture 1 Key Arithmetic Unit

Lecture 2 Verilog-Structural Modeling

Lecture 3 Verilog-Dataflow Modeling

Lecture 4 Verilog - Behavioral Modeling

Lecture 5 Register Transfers

Lecture 6 Sequencing and Control

Lecture 7 Memory Basics and Systems

Lecture 8 Computer Design Basics

Lecture 9 Instruction Set Architecture

Lecture 10 RISC Central Processing Unit

News Content Deadline / Date
Lecture update! 9 3/6, 2012

Lab_account

Example

Example

Digital Systems Design Lab

Lab01

Lab01

Lab02

Lab02

期末分組名單

成績

Lab1成績

Lab2成績

VIPLAB-poster

DSD_grade - Final

Teaching Assistant:
曾興嘉 sjzeng@viplab.cs.nctu.edu.tw

Phone: 03-5712121-59283

Lab: 電資大樓715 (Microelectronics and Information Systems Research Building, room 715)

Last Updated at 09:30 Jul 01, 2012