Digital System Design

教學目標

本課程以邏輯設計知識為基礎,探討數位系統的原理與設計。

課程綱要:

Lecture 0 Syllabus

Lecture 1 Key Arithmetic Units

Lecture 2 Verilog-Structural Modeling

Lecture 3 Verilog-Dataflow Modeling

Lecture 4 Verilog - Behavioral Modeling

Lecture 5 Registers and Register Transfers

Lecture 6 Sequencing and Control

Lecture 7 Computer Design Basics

Lecture 8 Instruction Set Architecture

Lecture 9 Filter and Transform Design

News Content Announcement Date
Have your attentions! All interested students must read Lectrue 0 especially last page and thank you very much. Feb. 12, 2017
Lecture upload! Lecture 0, 1, 2 Feb. 12, 2017
Lecture update! Lecture organization update Feb. 14, 2017
Lecture upload! Lecture 3 Mar. 3, 2017
Homework assignment! HW 1: Derive the Baugh-Wooley 8x8 partial product array from equations in lecture 1: duedate is March 17, 2017 Mar. 5, 2017
Homework assignment! HW 2: Derive sign-generate sign extension expression (5) from expression )1)~(4) for Booth multiplication in lecture 1: duedate is March 31, 2017 Mar. 12, 2017
Lecture upload! Lecture 4, 5, 6, 7, 8 Mar. 31, 2017
Lecture updated! Lecture 5 Apr. 14, 2017
Midterm Exam @ May 12(Friday), 2017! Lecture 1, 5, 6 and 7 Apr. 24, 2017
Final Report @ June 9, 2017! Technical Magainze and Paper Apr. 24, 2017
Lecture upload! Lecture 9 May 20, 2017

Teaching Assistant: 邱敬捷

Phone: 03-5712121-54742

Lab: EC-615

Last Updated at 06:13 Jun 05, 2017