VLSI Digital Signal Processing

Goal

Good understanding and design experience of VLSI signal processing algorithms and architecture and chips with applications to multimedia-communications systems through ASIC-, processor-, and platform-based approaches.

Outline

Lecture 0 Syllabus

Lecture 1 Introduction to Digital Signal Processing Systems

Lecture 2 Iteration Bound

Lecture 3 Pipelining and Parallel Processing

Lecture 4 Retiming

Lecture 5 Unfolding

Lecture 6 Folding

Lecture 7 Systolic Architecture Design

Lecture 8 Algorithmic Strength Reduction in Filters and Transforms

Lecture 9 Pipelined and Parallel Recursive and Adaptive Filters

Lecture 10 Bit-Level Arithmetic Architectures

Lecture 11 Low-Power CMOS VLSI Design

Lecture 12 Programmable Digital Signal Processors

 

Term Project Poster

[Poster file]

 

 

Action Item

News Content Date
Hw#1 STE1, STE2, STE3 10/9, 2008
Hw#2 STE4, STE5 10/16, 2008
Hw#3 2.1, 2.4 10/23, 2008
Hw#4 3.8, 3.9, 3.10 11/6, 2008
Hw#5 4.1, 4.8 11/13, 2008
Hw#6 Low power hw, 5.1, 5.3 11/20, 2008
Midterm Scope: Lecture 1~ 5, and Lecture 11 of the handout, Chapter 1 ~ Chapter 5 of the textbook. (星期四上午10:10 開始), 11/20, 2008
Midterm Report    
Term Project VLSI Architectures and EDA Tools Design  
     

Teaching Assistant: 吳廸優

e-mail: dywu@viplab.cs.nctu.edu.tw

Phone: 03-5712121-59283

Last Update: 10/29, 2008

Office Hour: 2:00pm ~ 3:00pm each Thursday at 工三館419室