VLSI Digital Signal Processing

教學目標

Good understanding and design experience of VLSI signal processing algorithms and architecture and chips with applications to multimedia-communications systems through ASIC, processor, and platform-based approaches.

課程綱要:

Lecture 0 Syllabus

Lecture 1 Introduction to Digital Signal Processing Systems

Lecture 2 Iteration Bound

Lecture 3 Pipelining and Parallel Processing

Lecture 4 Retiming

Lecture 5 Unfolding

Lecture 6 Folding

Lecture 7 Algorithmic Strength Reduction in Filters and Transforms

Lecture 8 Pipelined and Parallel Recursive and Adaptive Filters

Lecture 9 Low-Power CMOS VLSI Design

Lecture 10 Programmable Digital Signal Processors

Lecture 11 Introduction to 3D Graphics Processing Flow

Lecture 12 Lecture 12 Introduction to GPU Hardware

Lecture 13 Geometry Subsystem Design

News Content Deadline / Date
Site online Content 9/14, 2015
Upload Lecture 1 9/22, 2015
Upload Lecture 2 9/23, 2015
Upload Lecture 3 10/16, 2015
Upload Lecture 4 10/18, 2015
Homework 1 3.8, 3.10 deadline: 11/6, 2015
Upload Lecture 5 10/28, 2015
Upload Lecture 6 10/30, 2015
Upload Lecture 7 10/30, 2015
Homework 2 C=2 on the handout deadline: 11/20, 2015
Midterm Report Select one paper study and please send me for confirmation deadline: 11/23, 2015
Midterm Report Presentation Schedule 1. 11/27(五): 王釋興、蕭子杰 2. 12/1(二): 張庭菡、郭啟烈 3. 12/4(五): 李嘉棋 Announced date: 11/20, 2015
Homework 3 Usuing unfolding technique to unfold original DFG on page 7 of Lecture 5 with J=2. Finally, please depict the DSP block diagram using input/output, adder, multiplier, and D flip-flop for two-unfolded DFG. deadline: 12/04, 2015
Upload Lecture 8 12/2, 2015
Upload Lecture 9 12/2, 2015
Upload Lecture 10 12/11, 2015

Teaching Assistant:
邱敬捷 ccchiu(at)viplab.cs.nctu.edu.tw

Phone: 03-5712121-59283

Lab: 電資大樓715 (Microelectronics and Information Systems Research Building, room 715)

Last Updated at 08:00 Jan 01, 1970