VLSI Digital Signal Processing

教學目標:

Good understanding and design experience of VLSI signal processing algorithms and architecture and chips with applications to multimedia-communications systems through ASIC, processor, and platform-based approaches.

課程綱要

Lecture 0 Syllabus

Lecture 1 Introduction to Digital Signal Processing Systems

Lecture 2 Iteration Bound

Lecture 3 Pipelining and Parallel Processing

Lecture 4 Retiming

Lecture 5 Unfolding

Lecture 6 Folding

Lecture 7 Systolic Architecture Design

Lecture 8 Fast Convolution

Lecture 9 Algorithmic Strength Reduction in Filters and Transforms - Part I

Lecture 10 Pipelined and Parallel Recursive and Adaptive Filters

Lecture 11 Bit-Level Arithmetic Architectures

Lecture 12 Low-Power Design

Lecture 13 Programmable Digital Signal Processors

HW#1 Reference Solution

HW#2 Reference Solution

HW#3 Reference Solution

HW#4 Reference Solution

HW#5 Reference Solution

期中考於5/7, 2010(Friday CD)舉行,考試範圍為課本1~5章與講義1~5章

News Content Deadline / Date
update Lecture 3 3/25
update Lecture 4 3/25
HW#1 1.1, 1.2, 1.3 (handout) 3/19
HW#2 1.4, 1.5 (handout) 3/26
HW#3 2.1, 2.4 (text book) 4/2
HW#4 3.4, 3.5, 3.10 (text book) 4/9
HW#3 2.1, 2.4 (text book) 4/9 (postpone)
HW#4 3.4, 3.5, 3.10 (text book) 4/16 (postpone)
HW#5 4.2, 4.3, 4.8 (text book) 4/23
update Lecture 5 4/13
Midterm Text: Chapter 1~ Chapter 5, Handout: Lecture 1~ Lecture 5 5/7 (Friday CD)
update Lecture 9 - Part I 4/22
update HW#1~5 Reference Solution 5/4
update Lecture 9 - Part I 5/19
update Lecture 6 5/20
update Lecture 6 5/25
update Lecture 6 6/9
update Lecture 7 6/11
update Lecture 12 6/11
update Lecture 7 6/12
update Lecture 13 6/17
update Lecture 7 6/18
update Lecture 10 6/24

Office Hour: Wed AM10:00-AM12:00

Teaching Assistant:

吳迪優 dywu(at)viplab.cs.nctu.edu.tw

陳姵妤 pychen(at)viplab.cs.nctu.edu.tw

Phone: 03-5712121-59283

Lab: 電資大樓715

Last Update: 6/24, 2010