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Journal Paper
  1. L. D. Van, P. Y. Huang, and T. C. Lu, "Cost-effective and variable-channel FastICA hardware architecture and implementation for EEG signal processing," Journal of Signal Processing Systems, vol. 82, pp. 91-113, issue 1, Jan, 2016. (SCI, Full Paper) [PDF]

  2. I. H. Khoo, H. C. Reddy, L. D. Van, and C. T. Lin, "General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry," Multidimensional Systems and Signal Processing, 25, pp. 795-828, 2014. (SCI, Full Paper) [PDF]

  3. L. D. Van, D. Y. Wu, and C. S. Chen, "Energy-efficient FastICA Implementation for biomedical signal separation," IEEE Trans. Neural Networks, vol. 22, no. 11, pp. 1809-1822, Nov. 2011. (SCI, Full Paper) [PDF]

  4. L. D. Van , and T. Y. Sheu, "A power-area efficient geometry engine with low-complexity subdivision algorithm for 3D graphics system," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 58, no. 9, pp. 2211-2224, Sep. 2011. (SCI, Full Paper) ) [PDF]

  5. D. Y. Wu and L. D. Van, "Efficient detection algorithms for MIMO communication systems," Journal of Signal Processing Systems, vol. 62, issue 3, pp. 427-442, Mar. 2011. (SCI, Full Paper) [PDF]

  6. P. Y. Chen, L. D. Van, I. H. Khoo, H. C. Reddy, C. T. Lin, "Power-efficient and cost-effective 2-D symmetry filter architectures," IEEE Trans. Circuits Syst. I, vol. 58, no. 1, pp. 112-125, Jan. 2011. (SCI, Full Paper) [PDF]

  7. J. H. Tu and L. D. Van, "Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers," IEEE Trans. Computers, vol. 58, no. 10, pp. 1346-1355, Oct. 2009. (SCI, Full Paper) [PDF]

  8. C. T. Lin, Y. C. Yu, and L. D. Van, "Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor," IEEE Trans. VLSI Syst., vol. 16, no. 8, pp. 1058-1071, Aug. 2008. (SCI, Full Paper) [PDF]

  9. L. D. Van, C. T. Lin, and Y. C. Yu, VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 8, pp. 1644-1652, Aug. 2007. (SCI, Full Paper) [PDF]

  10. M. A. Song, L. D. Van, and S. Y. Kuo, "Adaptive low-error fixed-width Booth multipliers," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 6, pp. 1180-1187, Jun. 2007. (SCI, Full Paper) [PDF]

  11. L. D. Van and C. C. Yang, “Generalized low-error area-efficient fixed-width multipliers,” IEEE Trans. Circuits Syst. I, vol. 52, pp. 1608-1619, Aug. 2005. (SCI, Full Paper) [PDF]

  12. L. D. Van, "A new 2-D systolic digital filter architecture without global broadcast," IEEE Trans. VLSI Syst., vol. 10, pp. 477-486, Aug. 2002. (SCI, Full Paper) [PDF]

  13. L. D. Van and W. S. Feng, "An efficient systolic architecture for the DLMS adaptive filter and its applications," IEEE Trans. Circuits Syst. II, vol. 48, pp. 359-366, April 2001. (SCI, Full Paper) [PDF]

  14. L. D. Van, S. S. Wang, and W. S. Feng, "Design of the lower-error fixed-width multiplier and its application", IEEE Trans. Circuits Syst. II, vol. 47, pp. 1112-1118, Oct. 2000. (SCI, Brief) [PDF]
Book Edited
  1. Intel Atom Platform: Intelligent Systems Development and Applications, Editor: Lan-Da Van, Library & Book, 2014. (in Traditional Chinese, Sponsored by Intel, ISBN 978-986-90988-3-0)

International Conferences
  1. P. Y. Chen, L. D. Van, H. C. Reddy, and I. H. Khoo, "Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis," in Proc. IEEE International Conference on ASIC (ASICON), accepted, Oct. 2017, Guiyang, China. [PDF]

  2. P. Y. Chen, L. D. Van, H. C. Reddy, and I. H. Khoo, "New 2-D quadrantal- and diagonal-symmetry filter architectures using delta operator," in Proc. IEEE International Conference on ASIC (ASICON), accepted, Oct. 2017, Guiyang, China. [PDF]

  3. Z. Z. Wu, C. W. Wu, L. D. Van, and Y. C. Tseng, "Qnalyzer: Queuing recognition using accelerometer and Wi-Fi signals," in Proc. IEEE Global Communications Conference (GLOBECOM), accepted, Dec. 2017, Singapore. [PDF]

  4. P. Y. Chen, L. D. Van, H. C. Reddy, and I. H. Khoo, "New 2-D filter architectures with quadrantal symmetry and qctagonal symmetry and their error analysis," in Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 265-268, Aug. 2017, Boston, USA. [PDF]

  5. X. Zhang, C. W. Wu, P. Fournier-Viger, L. D. Van, Y. C. Tseng, "Analyzing students' attention in class using wearable device," in Proc. IEEE International Symposium on a World of Wireless, Mobile and Multimedia Networks (WoWMoM), accepted, Jun. 2017, Macau, China. [PDF]

  6. T. H. Wu, C. H. Chang, Y. W. Lin, L. D. Van, and Y. B. Lin, "Intelligent plant care hydroponic box using IoTtalk," in Proc. IEEE International Conference on Internet of Things (iThings), Dec., 2016, pp. 398-401, Chengdu, China. [PDF]

  7. T. C. Lu, P. Y. Chen, S. W. Yeh, and L. D. Van, "Multiple stopping criteria and high-precision EMD architecture implementation for Hilbert-Huang transform," in Proc. IEEE Biomedical Circuits Syst. (BioCAS), Oct. 2014, pp. 200-203, Lausanne, Switzerland. [PDF]

  8. J. W. Qiu, T. H. Chiang, C. C. Lo, L. M. Lin, L. D. Van, Y. C. Tseng, and Y. T. Ching, "Continuous human location and posture tracking by multiple depth sensors," in Proc. IEEE International Conference on Internet of Things (iThings), Sep., 2014, pp. 155-160, Taipei, Taiwan. [Best Paper Award] [PDF]

  9. T. C. Lu, S. H. Hsu, S. J. Tzeng, C. M. Chang, and L. D. Van, "Implementation of a human-centric GUI for next-generation intensive care unit," in Proc. IEEE International Conference on Consumer Electronics-Taiwan, May, 2014, pp. 179-180, Taipei, Taiwan. [PDF]

  10. P. Y. Chen, L. D. Van, H. C. Reddy, and I. H. Khoo, "Area-efficient 2-D digital filter architectures possessing diagonal and four-fold rotational symmetries," in Proc. International Conference on Information, Communications and Signal Processing (ICICS), Dec. 2013, pp. 1-4, Tainan, Taiwan.

  11. I. H. Khoo, H. C. Reddy, L. D. Van, and C. T. Lin, "Design of 2-D digital filters with almost quadrantal symmetric magnitude response without 1-D separable denominator factor constraint," in Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2013, pp. 999-1002, Ohio, USA. [PDF]

  12. I. H. Khoo, H. C. Reddy, L. D. Van, and C. T. Lin, "Delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the quadrantal symmetry," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May. 2012, pp. 3190-3193, Seoul, Korea. [PDF]

  13. T. C. Lu, L. D. Van, C. S. Lin, and C. M. Huang, "A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications,"in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Sep. 2011. [PDF]

  14. I. H. Khoo, H. C. Reddy, L. D. Van, C. T. Lin, "Generalized formulation of 2-D filter structures without global broadcast for VLSI implementation," in Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2010, pp. 426-429, Seattle, USA. [PDF]

  15. T. Y. Sheu, L. D. Van, T. R. Jung, C. W. Lin, and T. W. Chang, "Low complexity subdivision algorithm to approximate Phong shading using forward difference," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2009, pp. 2373-2376, Taipei, Taiwan. [PDF]

  16. P. Y. Chen, L. D. Van, and H. C. Reddy and C. T. Lin, "A new VLSI 2-D fourfold-rotational-symmetry filter architecture design," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2009, pp. 93-96, Taipei, Taiwan. [PDF]

  17. I. H. Khoo, H. C. Reddy, L. D. Van, and C. T. Lin, "2-D digital filter architectures without global broadcast and some symmetry applications," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2009, pp. 952-955, Taipei, Taiwan. [PDF]

  18. L. Y. Lin, H. K. Lin, C. Y. Wang, L. D. Van, and J. Y. Jou, "Hierarchical architecture for network-on-chip platform, in Proc. VLSI-DAT, Apr. 2009, pp. 343-346, Hsinchu, Taiwan. [PDF]

  19. W. C. Huang, S. H. Hung, J. F. Chung, M. H. Chang,L. D. Van, and C. T. Lin, "FPGA implementation of 4-Channel ICA for on-line EEG signal separation," in Proc. IEEE Int. Biomedical Circuits Syst. Conference (BioCAS), Nov. 2008, pp. 65-68, Baltimore, USA. [PDF]

  20. P. Y. Chen,L. D. Van, and H. C. Reddy and C. T. Lin, "A new VLSI 2-D diagonal-symmetry filter architecture design," in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2008, pp. 320-323, Macao, China. [PDF]

  21. D. Y. Wu, L. D. Van, "A grouped-iterative framework for MIMO detection," in Proc. IEEE Vehicle Technology Conference (VTC), Sep. 2008, accepted, Calgary, Canada. [PDF]

  22. T. R. Jung, T. Y. Sheu, C. W. Lin, L. D. Van, W. C. Fang, "Design of multi-mode depth buffer compression for 3D graphics system," in Proc. IEEE Int. Conf. Multimedia and Expo. (ICME), Jun. 2008, pp. 789-792, Hannover, Germany. [PDF]

  23. T. R. Jung, L. D. Van, W. C. Fang, T. Y. Sheu, "Reconfigurable depth buffer compression design for 3D graphics system," in Proc. Int. Conf. MUE, Apr. 2008, pp. 470-474, Busan, Korea. [PDF]

  24. C. W. Hsueh, J. F. Chung, L. D. Van, C. T. Lin, "Anticipatory access pipeline design for phased cache," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2008, pp. 2342-2345, Seattle, USA. [PDF]

  25. C. C. Huang, S. H. Hung, J. F. Chung, L. D. Van, C. T. Lin, "Front-end amplifier of low-noise and tunable BW/Gain for portable biomedical signal acquisition," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2008, pp. 2717-2720, Seattle, USA. [PDF]

  26. C. T. Lin, L. W. Ko, B. C. Kuo, S. F. Liang, K. L. Lin, I. F. Chung, L. D. Van, "Classification of driver's cognitive responses using nonparametric single-trial EEG analysis," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2007, pp. 2019-2023, New Orleans, USA. [PDF]

  27. L. D. Van, H. F. Luo, N. S. Chang, C. M. Huang, "A cost-effective reconfigurable accelerator for platform-based SOC design," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2006, pp. 1977-1980, Greece. [PDF]

  28. C. T. Lin, Y. C. Yu, L. D. Van, "A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2006, pp. 4523-4526, Greece. [PDF]

  29. C. M. Huang, K. J. Lee, C. C. Yang, W. S. Hu, S. S. Wang, J. B. Chen, C. S. Chen, L. D. Van, C. M. Wu, W. C. Tsai, J. Y. Jou,, "Multi-Project System-on-Chip (MP-SoC): A novel test vehicle for SoC silicon prototyping," in Proc. IEEE Int. SOC Conf. (SOCC), Sep. 2006, Texas, USA. (Invited Paper) [PDF]

  30. L. D. Van, Y. C. Yu, C. M. Huang, C. T. Lin, "Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture," in Proc. IEEE Workshop on Signal Processing Systems (SiPS), Nov. 2005, pp. 579-584, Athens, Greece. [PDF]

  31. H. Y. Chao, J. S. Wang, C. M. Wu, C. M. Huang, L. D. Van, "High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS," in Proc. IEEE Int. Conf. Multimedia and Expo. (ICME), July 2005, Amsterdam, Netherlands. [PDF]

  32. Y. C. Fan, L. D. Van, C. M. Huang, H. W. Tsao, "Hardware-efficient architecture design of wavelet-based adaptive visible watermarking," in Proc. IEEE Int. Symp. Consume Electronics (ISCE), June 2005, pp. 399-403, Macau. [PDF]

  33. M. A. Song, L. D. Van, C. C. Yang, S. C. Chiu, S. Y. Kuo, "A framework for the design of error-aware power-efficient fixed-width Booth multipliers," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2005, pp. 81-84, Kobe, Japan. [PDF]

  34. C. A. Tsai, Y. T. Chou, Y. T. Chang, L. D. Van, C. M. Huang, "ARM-Based SoC Prototyping Platform Using Aptix," in ICEER, March 2005, Tainan, Taiwan. [Best Poster Award] [PDF]

  35. M. A. Song, L. D. Van, T. C. Huang, and S. Y. Kuo, "A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers", IEEE Int. Midwest Symp. Circuits Syst. (MWSCAS), July 2004, vol. 1, pp. 9-12, Japan. [Best Student Paper Nomination] [PDF]

  36. L. D. Van, H. F. Luo, C. M. Wu, W. S. Hu, C. M. Huang, and W. C. Tsai, "A high-performance area-aware DSP processor architecture for video codecs," in Proc. IEEE Int. Conf. Multimedia and Expo. (ICME), Jun. 2004, vol. 3, pp. 1499-1502, Taipei, Taiwan. [PDF]

  37. L. D. Van and C. C. Yang, "High-speed area-efficient recursive DFT/IDFT architectures," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2004, vol. 3, pp. 357-360, Vancouver, Canada. [PDF]

  38. M. A. Song, L. D. Van, T. C. Huang and S. Y. Kuo, "A low-error and area-time efficient fixed-width Booth multiplier," to appear in Proc. IEEE Int. Midwest Symp. Circuits Syst. (MWSCAS), Dec. 2003, vol. 2, pp. 590-593, Egypt. [PDF]

  39. L. D. Van and C. H. Chang, "Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR)," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2002, vol. 1, pp. 37-40, Phoenix , Arizona. [PDF]

  40. L. D. Van and S. H. Lee, "A generalized methodology for lower-error area-efficient fixed-width multipliers," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2002, vol. 1, pp. 65-68, Phoenix , Arizona . [PDF]

  41. C. C. Tang, W. S. Lu, L. D. Van, and W. S. Feng, "A 2.4 GHz CMOS down-conversion doubly balanced mixer with low supply voltage," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2001, vol. 4, pp. 794-797, Sydney , Australia . [PDF]

  42. L. D. Van, S. Tenqchen, C. H. Chang, and W. S. Feng, "A new 2-D digital filter using a locally broadcast scheme and its cascade form," in Proc. IEEE Asia Pacific Conf. on Circuits Syst. (APCCAS), Dec. 2000, pp. 579-582, Tianjin, China. [PDF]

  43. L. D. Van and W. S. Feng, "Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters," in Proc. IEEE Asia Pacific Conf. on Circuits Syst. (APCCAS), Dec. 2000, pp. 399-402, Tianjin, China. [PDF]

  44. L. D. Van, C. C. Tang, S. Tenqchen, and W. S. Feng, "A new VLSI architecture without global broadcast for 2-D systolic digital filters ," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2000, vol. 1, pp. 547-550, Geneva , Switzerland . [PDF]

  45. L. D. Van, S. S. Wang, S. Tenqchen, W. S. Feng, and B. S. Jeng, "Design of a lower error fixed-width multiplier for speech processing application," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 1999, vol. 3, pp. 130-133, Orlando , Florida . [PDF]

  46. L. D. Van, S. Tenqchen, C. H. Chang, and W. S. Feng, "A tree-systolic array of DLMS adaptive filter," in Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP), Mar. 1999, vol. 3, pp. 1253-1256, Phoenix, Arizona. [PDF]
Patents
  1. C. M. Huang, C. C. Yang, J. Y. Jou,, K. J. Lee,L. D. Van, "Multi-project system-on-chip and its method ", US Patent, No: 7,571,414 B2 Aug., 2009.

  2. 黃俊銘、楊智喬、周景揚、李昆忠、范倫達, "多計畫系統單晶片平台及其設計方法", ROC Patent, No: I306211, Feb. 2009.
Dissertation and Thesiss
  1. Lan-Da Van, Design of Efficient VLSI Architectures: Multiplier, 2-D Digital Filter, and Adaptive Digital Filter, Ph. D. Dissertation, Dept. of the Electrical Engineering, National Taiwan University , Taipei , Taiwan , R.O.C., 2001.

  2. Lan-Da Van, New Architectures and Implementations of FIR Filters Using Efficient Multipliers, Master Thesis, Dept. of the Electrical Engineering, Tatung Institute of Technology, Taipei , Taiwan , R.O.C., 1997.
Article (In Traditional Chinese)
  1. 范倫達、林進燈, "參加2008年『大學優良教師傳承』研討會之我思", 交大有聲, 431期, pp. 66-66, Dec. 2008. [This session is orgainzed by 國立交通大學 許炳堅 榮譽教授]

  2. 許藤耀、林丞蔚、鍾宗融、張庭維、涂晉豪、范倫達, "3D圖學渲染演算法之簡介與研究", 影像與識別, vol.14, no. 2, pp. 61-69, 2008.

  3. 黃俊銘、楊智喬、胡文祥、王旭昇、陳正斌、陳麒旭、吳建明、范倫達、周景揚, "計畫系統單晶片(Multi-Project System-on-Chip, MP-SoC)介紹", 電子月刊, pp. 116-127, May, 2007.
Submitted and under Review Manuscript
  1. C. C. Chiu, L. D. Van , and Y. S. Lin, "Efficient progressive radiance estimation engine architecture and implementation for progressive photon mapping," Submitted to IEEE Trans. Circuits Syst. I: Regular Papers, June 2016.

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Last Updated at 13:16 Aug 16, 2017

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